1. Field of the Invention
The present invention relates to a packet communication apparatus for processing fixed-length packets and, in particular, to a packet communication apparatus wherein reading and writing of packet data are executed relative to a storage circuit.
2. Description of the Related Art
In addition to merely switching or exchanging packets, a fixed-length packet exchange implements predetermined processing with respect to packet data of the packets. For example, when a charge is determined according to the number of switched packets, the packet exchange counts the number of switched packets per destination and charges a sender for it. The packet exchange also obtains predetermined statistical information from the packet data of the packets. Further, the packet exchange detects and corrects an error using data which is attached to each packet for error detection and correction.
For accomplishing the foregoing processing including the packet switching, the packet exchange includes a storage circuit for storing packet data of received packets and other data. The packet exchange further includes a first processing circuit for reading packet data from each packet, reading necessary data from the storage circuit, performing processing such as routing and error detection and correction, and writing resultant data into the storage circuit and the corresponding packet. The processing implemented by the first processing circuit is essential upon receipt of each packet for the purpose of a packet transfer. The packet exchange further includes a second processing circuit which performs reading and writing relative to the storage circuit for processing data stored therein as required by a control system of the packet exchange. The processing implemented by the second processing circuit is not essential upon receipt of each packet. Thus, the processing implemented by the first processing circuit has higher priority than the processing implemented by the second processing circuit.
The storage circuit is designed to prohibit simultaneous accesses thereto by the first and second processing circuits. Thus, the first and second processing circuits should selectively access the storage circuit. As described above, the processing implemented by the first processing circuit has the higher priority than the processing implemented by the second processing circuit. Under the circumstances, according to the conventional technique, only the first processing circuit is allowed to access the storage circuit during a packet processing time (time allowed for exchanging each packet), and the second processing circuit is allowed to access the storage circuit only while there exist no packets to be exchanged.
However, according to the conventional technique, the second processing circuit can not access the storage circuit at all if packets are consecutively exchanged. As a result, an access to the storage circuit by the second processing circuit should await for a long time until there exist no packets to be exchanged. This causes a problem that execution of the predetermined processing by the second processing circuit is likely to be delayed. Further, for the same reason, there is also a problem that if the foregoing storage circuit is a DRAM (dynamic random access memory), the DRAM can not be refreshed periodically.
Therefore, it is an object of the present invention to provide an improved packet communication apparatus.
According to one aspect of the present invention, there is provided a packet communication apparatus for processing consecutive fixed-length packets, the apparatus comprising a storage circuit; a first processing circuit which accesses the storage circuit for executing first processing with respect to data obtained from each of the packets; a second processing circuit which accesses the storage circuit for executing second processing with respect to data stored in the storage circuit; and an allocation circuit for executing access time allocation with respect to a packet processing time allowed for processing each of the packets, the allocation circuit allocating a first time of the packet processing time to the first processing circuit for accessing the storage circuit and a second time of the packet processing time to the second processing circuit for accessing the storage circuit, the first time and the second time prevented from overlapping with each other.
It may be arranged that the storage circuit is a DRAM, and the second processing circuit refreshes the DRAM during the second time.
It may be arranged that the packet communication apparatus further comprises a producing circuit which receives a first packet synchronizing signal having first signal components each indicative of a boundary time point between the adjacent packets and produces a second packet synchronizing signal based on the first packet synchronizing signal, wherein the producing circuit, in response to one of the first signal components, produces in sequence second signal components of the second packet synchronizing signal at a given cycle corresponding to the packet processing time, the given cycle being free of an influence of the first signal components subsequent to the one of the first signal components, and wherein the allocation circuit executes the access time allocation based on the second packet synchronizing signal.
It may be arranged that the producing circuit comprises a counter which produces in sequence the second signal components at the given cycle in response to the one of the first signal components, and a control circuit which inhibits any of the first signal components being asynchronous with the given cycle from being inputted into the counter.
It may be arranged that the packet communication apparatus further comprises a producing circuit which receives a first packet synchronizing signal having first signal components each indicative of a boundary time point between the adjacent packets and produces a second packet synchronizing signal based on the first packet synchronizing signal, wherein the producing circuit produces second signal components of the second packet synchronizing signal in response to the first signal components such that any of the first signal components which is advanced in phase relative to the packet processing time is prevented from reflecting on the second packet synchronizing signal, and wherein the allocation circuit executes the access time allocation based on the second packet synchronizing signal.
It may be arranged that the producing circuit comprises a control circuit which receives the first signal components, and a first counter which produces each of the second signal components in response to a corresponding input from the control circuit, and that the control circuit inhibits any of the first signal components, which is advanced in phase relative to the packet processing time, from being inputted into the first counter.
It may be arranged that the producing circuit further comprises a second counter which, in response to an input of each of the first signal components, outputs a corresponding signal component to the control circuit, while the second counter outputs a signal component to the control circuit at a given cycle corresponding to the packet processing time when no input is given to the second counter.
According to another aspect of the present invention, there is provided a packet communication apparatus for processing consecutive fixed-length packets, the apparatus comprising a DRAM; a processing circuit which accesses the DRAM for processing data obtained from each of the packets; a refresh circuit for refreshing the DRAM; and an allocation circuit for executing access time allocation with respect to a packet processing time allowed for processing each of the packets, the allocation circuit allocating a first time of the packet processing time to the processing circuit for accessing the DRAM and a second time of the packet processing time to the refresh circuit for refreshing the DRAM, the first time and the second time prevented from overlapping with each other.